Module 06: GPU Kernels and Compilers

Prerequisites

• Complete Inference and Serving.
• Be able to estimate bytes moved, operations performed, and tensor layouts.

Outcomes

• Explain GPU hierarchy, warps/wavefronts, memory spaces, occupancy, and synchronization.
• Use profiling evidence to distinguish bandwidth, latency, and compute limits.
• Describe how kernel DSLs and compilers transform tensor programs.

Ordered free resources

1. CUDA C++ Programming Guide · Tier A · Documentation / reference / code — build the vendor-specific execution and memory model.
2. HIP Documentation · Tier A · Documentation / reference / code — compare portable concepts and hardware terminology.
3. Triton Language Tutorials · Tier A · Documentation / tutorials / labs — express tiled kernels with explicit program instances.
4. Apache TVM Documentation · Tier A · Documentation / tutorials / code — study scheduling, lowering, and generated code.
5. Deep Learning Systems · Tier A · Course / video / labs — reconnect kernels to framework execution.

Checkpoints

• Draw and explain the hierarchy in CUDA Execution Concepts.
• Predict coalescing and reuse for two matrix layouts.
• Compare a simple reference operation with one fused or tiled implementation.

Self-tests

1. Why can high occupancy fail to imply high performance?
2. Which synchronization scope is valid inside one thread block?
3. What evidence shows that fusion reduced total memory traffic?

Capstone

Optimize one small GPU operation using either CUDA/HIP, Triton, or a compiler schedule. Record the baseline, bottleneck hypothesis, correctness checks, profile evidence, speedup boundaries, and portability limitations.

Next: Distributed Systems